module MYFIFO(
  input          clock,
  input          reset,
  input  [511:0] io_memData,
  input          io_memValid,
  input          io_advance_fifo,
  output [71:0]  io_tile,
  output         io_ready,
  output         io_full
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [511:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [95:0] _RAND_7;
  reg [95:0] _RAND_8;
  reg [95:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg  startup; // @[MYFIFO.scala 34:30]
  reg [511:0] topBuf_0; // @[MYFIFO.scala 38:29]
  reg  droptile; // @[MYFIFO.scala 41:31]
  reg  full; // @[MYFIFO.scala 62:27]
  reg  empty2; // @[MYFIFO.scala 75:29]
  wire  _T_4 = full & empty2; // @[MYFIFO.scala 83:26]
  reg  empty3; // @[MYFIFO.scala 76:29]
  reg  empty4; // @[MYFIFO.scala 77:29]
  wire  _GEN_12 = empty4 & ~empty3 ? 1'h0 : droptile; // @[MYFIFO.scala 91:39]
  wire  _GEN_18 = empty3 & ~empty2 ? 1'h0 : _GEN_12; // @[MYFIFO.scala 87:39]
  wire  _GEN_26 = full & empty2 ? 1'h0 : _GEN_18; // @[MYFIFO.scala 83:37]
  wire  clearDrop = ~startup ? 1'h0 : _GEN_26; // @[MYFIFO.scala 79:23]
  wire  _GEN_0 = clearDrop ? 1'h0 : droptile; // @[MYFIFO.scala 46:32 47:26 41:31]
  wire  _GEN_1 = io_advance_fifo | _GEN_0; // @[MYFIFO.scala 44:30 45:26]
  wire  clearTop = ~startup ? 1'h0 : _T_4; // @[MYFIFO.scala 79:23]
  wire  _GEN_5 = clearTop ? 1'h0 : full; // @[MYFIFO.scala 66:31 67:22 62:27]
  wire  _GEN_6 = io_memValid | _GEN_5; // @[MYFIFO.scala 64:52 65:22]
  reg [71:0] buf2; // @[MYFIFO.scala 71:27]
  reg [71:0] buf3; // @[MYFIFO.scala 72:27]
  reg [71:0] buf4; // @[MYFIFO.scala 73:27]
  wire  _GEN_7 = droptile | empty4; // @[MYFIFO.scala 95:30 96:24 77:29]
  wire [71:0] _GEN_9 = empty4 & ~empty3 ? buf3 : buf4; // @[MYFIFO.scala 91:39 92:22 73:27]
  wire  _GEN_10 = empty4 & ~empty3 ? 1'h0 : _GEN_7; // @[MYFIFO.scala 91:39 93:24]
  wire  _GEN_11 = empty4 & ~empty3 | empty3; // @[MYFIFO.scala 91:39 94:24 76:29]
  wire  _GEN_14 = empty3 & ~empty2 ? 1'h0 : _GEN_11; // @[MYFIFO.scala 87:39 89:24]
  wire  _GEN_15 = empty3 & ~empty2 | empty2; // @[MYFIFO.scala 87:39 90:24 75:29]
  wire  _GEN_17 = empty3 & ~empty2 ? empty4 : _GEN_10; // @[MYFIFO.scala 77:29 87:39]
  wire [511:0] _GEN_19 = full & empty2 ? topBuf_0 : {{440'd0}, buf2}; // @[MYFIFO.scala 83:37 84:22 71:27]
  wire  _GEN_21 = full & empty2 ? 1'h0 : _GEN_15; // @[MYFIFO.scala 83:37 86:24]
  wire  _GEN_23 = full & empty2 ? empty3 : _GEN_14; // @[MYFIFO.scala 76:29 83:37]
  wire  _GEN_25 = full & empty2 ? empty4 : _GEN_17; // @[MYFIFO.scala 77:29 83:37]
  wire  _GEN_27 = ~startup | _GEN_21; // @[MYFIFO.scala 79:23 80:24]
  wire  _GEN_28 = ~startup | _GEN_23; // @[MYFIFO.scala 79:23 81:24]
  wire  _GEN_29 = ~startup | _GEN_25; // @[MYFIFO.scala 79:23 82:24]
  wire [511:0] _GEN_30 = ~startup ? {{440'd0}, buf2} : _GEN_19; // @[MYFIFO.scala 79:23 71:27]
  wire [511:0] _GEN_35 = reset ? 512'h0 : _GEN_30; // @[MYFIFO.scala 71:{27,27}]
  assign io_tile = buf4; // @[MYFIFO.scala 102:17]
  assign io_ready = startup & ~empty4 & ~droptile; // @[MYFIFO.scala 100:42]
  assign io_full = full; // @[MYFIFO.scala 101:17]
  always @(posedge clock) begin
    if (reset) begin // @[MYFIFO.scala 34:30]
      startup <= 1'h0; // @[MYFIFO.scala 34:30]
    end else begin
      startup <= 1'h1; // @[MYFIFO.scala 34:30]
    end
    if (reset) begin // @[MYFIFO.scala 38:29]
      topBuf_0 <= 512'h0; // @[MYFIFO.scala 38:29]
    end else if (io_memValid) begin // @[MYFIFO.scala 51:26]
      topBuf_0 <= io_memData; // @[MYFIFO.scala 58:31]
    end
    if (reset) begin // @[MYFIFO.scala 41:31]
      droptile <= 1'h0; // @[MYFIFO.scala 41:31]
    end else begin
      droptile <= _GEN_1;
    end
    if (reset) begin // @[MYFIFO.scala 62:27]
      full <= 1'h0; // @[MYFIFO.scala 62:27]
    end else begin
      full <= _GEN_6;
    end
    empty2 <= reset | _GEN_27; // @[MYFIFO.scala 75:{29,29}]
    empty3 <= reset | _GEN_28; // @[MYFIFO.scala 76:{29,29}]
    empty4 <= reset | _GEN_29; // @[MYFIFO.scala 77:{29,29}]
    buf2 <= _GEN_35[71:0]; // @[MYFIFO.scala 71:{27,27}]
    if (reset) begin // @[MYFIFO.scala 72:27]
      buf3 <= 72'h0; // @[MYFIFO.scala 72:27]
    end else if (!(~startup)) begin // @[MYFIFO.scala 79:23]
      if (!(full & empty2)) begin // @[MYFIFO.scala 83:37]
        if (empty3 & ~empty2) begin // @[MYFIFO.scala 87:39]
          buf3 <= buf2; // @[MYFIFO.scala 88:22]
        end
      end
    end
    if (reset) begin // @[MYFIFO.scala 73:27]
      buf4 <= 72'h0; // @[MYFIFO.scala 73:27]
    end else if (!(~startup)) begin // @[MYFIFO.scala 79:23]
      if (!(full & empty2)) begin // @[MYFIFO.scala 83:37]
        if (!(empty3 & ~empty2)) begin // @[MYFIFO.scala 87:39]
          buf4 <= _GEN_9;
        end
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  startup = _RAND_0[0:0];
  _RAND_1 = {16{`RANDOM}};
  topBuf_0 = _RAND_1[511:0];
  _RAND_2 = {1{`RANDOM}};
  droptile = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  full = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  empty2 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  empty3 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  empty4 = _RAND_6[0:0];
  _RAND_7 = {3{`RANDOM}};
  buf2 = _RAND_7[71:0];
  _RAND_8 = {3{`RANDOM}};
  buf3 = _RAND_8[71:0];
  _RAND_9 = {3{`RANDOM}};
  buf4 = _RAND_9[71:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
